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A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS
Journal article   Peer reviewed

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

Perry Heedley, Kenneth Dyer, Thomas Matthews, Patrick Isakanian and Chuc Thanh
Analog integrated circuits and signal processing, Vol.56(1), pp.43-51
08/2008
DOI: https://doi.org/10.1007/s10470-007-9081-5
Handle:
https://hdl.handle.net/20.500.12741/rep:3769

Abstract

ADC Engineering Analog-to-digital conversion Signal, Image and Speech Processing Circuits and Systems CMOS integrated circuits Electronic and Computer Engineering Pipeline
An 8-b pipelined ADC constructed in 0.13-μm CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125 MS/s while consuming 30 mW from 1.8-V and 1.2-V supplies. Active area is 0.4 mm2. Numerous challenges associated with this choice of process technology were overcome, such as limited dynamic range, copper metallization and the effects of gate oxide leakage.

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