Abstract
In this project a hardware Hash Tree Engine (HTE) embedded within a secure processor is modeled and simulated that verifies the authenticity of untrusted memory accessed by the processor. The HTE maintains a Merkle Hash Tree to attest the integrity of data accessed from a range of untrusted memory addresses. The project investigates the worst case time required to authenticate a cache block accessed from the untrusted memory. The HTE, which uses the SHA 256 hashing algorithm and a separate cache memory, is modeled and simulated using Verilog HDL. The nodes of the hash tree and data are assumed to be stored in the untrusted memory space. The root hash of the hash tree, however, resides inside the trusted boundary of the secure processor package.