Abstract
A phase-locked loop (PLL) is a widely-used mixed-signal circuit that is used to create the precise clocks required on almost every integrated circuit. A PLL uses negative feedback to control an on-chip oscillator so that its frequency equals a multiple of a reference clock frequency provided from off-chip. The on-chip clock and the reference clock have a stable phase relationship. In recent years phase-locked loops have moved towards digital-intensive or all-digital designs due to advancements in CMOS technology which make these attractive in terms of area and power consumption. This project was to design and simulate a time-to-digital converter (TDC), which is a circuit used in an all-digital phase-locked loop. The TDC converts the phase difference between the on-chip clock and the reference clock into a digital code which is used to adjust the phase and frequency of the on-chip oscillator. Circuit schematics were designed for a time-to-digital converter in Cadence Virtuoso and simulated using the Spectre simulator in a 0.18um CMOS process. Simulations were performed to verify the performance across variations in process, supply voltage, and temperature.