Abstract
In the analog domain, there are critical components such as Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), and Phase-Locked Loops (PLLs) which plays an important role in various applications. One of the components (PLL) have an issue with power consumption and instability in the Voltage-Controlled Oscillator (VCO) when facing supply voltage fluctuations. These issues can degrade the performance of the entire PLL system. from the research paper “A FrequencyTunable Fractional N PLL for High Energy Physics Experiments,” this project highlights the importanceof a stable supply voltage for the VCO and achieving a frequency of 500MHz when the input frequency is given 100MHz. Inspired by the implementation of a lowdropout regulator (LDO) in that paper, this design demonstrates the integration of an LDO to stabilize the VCO’s supply voltage by achieving a constant and stable voltage of1.2V. The implementation is modeled in Verilog A, showcasing how the integration of an LDO optimizes VCO performance. Comparative simulations show the difference in output waveforms when the VCO operates with a standard supply voltage versus an LDO regulated supply. This project demonstrates the importance of stable voltage regulation for enhancing the efficiency and reliability of PLLs when a stable voltage is given to the VCO.