Abstract
Advancements in technology often offer solutions to many existing problems, but sometimes create few vulnerabilities. One such vulnerability during recent times is security concerns. Increasing data requirements and reduced access time for faster systems are addressed by new technologies using DRAM but raise security concerns like row hammering attacks. DRAM consists of millions of DRAM cells. The DRAM cell is made up of 1 Transistor and 1 capacitor. As the capacitor is involved, it must be refreshed at a particular time interval which is handled by the memory controller through auto refresh. Row hammering is a technique employed by the attacker that exploits a vulnerability in DRAM chips to corrupt data or gain unauthorized access to a system. The attacker repeatedly accesses rows of memory cells in a rapid and targeted manner, which can cause the bit values in adjacent rows to flip unexpectedly. This unintended behavior can be exploited by attackers to gain unauthorized access to data, escalate privileges, or cause system crashes. To reduce the row – hammering attacks an algorithm is implemented to keep track of the number of row accesses and activations to identify/estimate the rows that can be affected. Refresh mechanisms in DRAM are designed to mitigate the effects of charge leakage and prevent data corruption.