Abstract
Voltage-Controlled Oscillator (VCO)-based Analog-to-Digital Converters (ADCs) have emerged as a promising solution for digitizing analog signals, especially in advanced CMOS processes where traditional voltage-domain quantization faces significant challenges due to shrinking supply voltages. By converting input voltage variations into frequency or phase changes, VCO-based architectures shift the quantization process to the time domain, enabling efficient digitization through simple digital circuits. This approach capitalizes on the advantages of scaled CMOS technologies, such as the availability of high-speed, low-power transistors.
However, a critical limitation of VCO-based ADCs is the inherent non-linearity in their voltage-to-frequency (V-to-F) transfer characteristic. This non-linearity becomes particularly pronounced at higher input amplitudes, leading to distorted outputs and a constrained spurious-free dynamic range (SFDR), which limits their applicability in precision applications. In addition, VCO-based ADCs requires large CMOS active area on-chip especially for non-linearity correction techniques.
This thesis introduces a novel Time-Division Multiple Access (TDMA) VCO-based ADC architecture tailored for low-power, compact neural recording systems, specifically targeting Local Field Potential (LFP) and Action Potential (AP) detection in bio-sensor applications. The proposed architecture mitigates VCO non-linearity by ensuring operation within the small-signal linear region, achieved through amplitude reduction techniques. By employing a TDMA scheme, the system efficiently acquires signals from 16 neural electrodes, significantly enhancing power efficiency and enabling hardware sharing to minimize area overhead. This is particularly critical for micro-electrocorticography (µECoG) applications, where CMOS active area constraint is a major challenge.
Furthermore, the system incorporates motion artifact recording capabilities, enabling off-chip cancellation of motion-induced artifact noise. Designed in 65nm CMOS technology, the architecture achieves competitive per-channel area and power consumption while maintaining low input-referred noise levels across the neural recording band. This thesis not only presents a state-of-the-art neural recording solution but also provides a comprehensive performance evaluation, setting the stage for future innovations in neural interfacing technology.