Abstract
Very large-scale integration (VLSI) chip design industry is getting mature every day with application-specific integrated circuit (ASIC) design being incorporated in every industry. The high demand for these applications results in an increase in the system and System-on-Chip (SoC) design complexity, and in an apparent chip validation bottleneck. Moreover, incorporating complex system design in a single chip requires millions of hours to complete the design verification process. In practice, this might not be an option due to the limited window to market the system. In this project, we propose a system emulation tool based on programmable gate array (FPGA) emulation to aid in reducing the system design time. The proposed tool will be used to conduct several test scenarios to be run, which as a result, will lead to rigorous verification of the design architecture before tape-out and provide amble time for testing and software debugging.