Abstract
Common Channel Signaling #7 (also known as CCS#7 and SS#7) is widely used signaling protocol for the telecommunication as well as satellite communication. CCS#7 protocol uses packets instead of signals to minimize the latency between signaling points. CCS#7 comprises of various layers such as Message Transfer Protocol-1 (MTP-1), MTP-2, MTP-3 and User Part in its architecture. The objective of this project is to study and implement this protocol using System Verilog. This project is divided into various phases. The first phase includes the study of architecture and functionality of the protocol. The second phase includes the study of the error detection and correction methods employed in the MTP-2 layer. The third phase includes the design and simulation of the packet transmission between two signaling points. The implementation of the design is executed using the System Verilog Hardware Description Language (HDL) and uses Synopsys VCS and Design Vision tool for its compilation, debugging and functional verification. The design is divided into various small modules such as the Transmitter, Receiver, interfaces between User Part and MTP-3 layer as well as interface between two signaling points. Each part is designed using the Finite State Machines (FSM). The functionality for the design is verified in a test bench environment with different test cases. The results of simulation have been verified to be working accurately according to the specifications of the protocol.