Abstract
Data corruption during the transmission and reception of data because of noisy channel medium is the most common problem faced in digital communication system. Thus, it is hard to get the reliable communication. Thus, to get the error free communication we need Error correction code. BCH codes is an acronym for Bose, Ray – Chaudhuri, Hocquenghem, invented in 1960s and today they are used as a baseline for many recent Error Correcting Codes. BCH codes are powerful class of multiple error correction codes with well defined mathematical properties. BCH code is used to correct multiple random error patterns. The mathematical properties within which BCH codes are defined are the Galois Field or Finite Field Theory. The main focus of this project is to design encoder and decoder architecture for BCH codes. The design of an encoder is based on Liner Feed Back Shift Register used for polynomial division and the decoder design is based on ibm algorithm to correct the errors occurred during transmission. Also this project report contains comparison of BCH codes with other Error Correcting codes and gives the detailed explanation of salient feature of BCH codes. The combination of BCH codes and LDPC codes are used for error correction for satellite communication standards. The BCH codes architecture is described using hardware description language called Verilog and synthesized using Xilinx Webpack 10.1 ISE. The performance of the whole model is check in terms of simulation using Xilinx Modelsim.