Abstract
System performance relies heavily on Arithmetic Logic Unit (ALU) operations in the digital world. The ALU is a critical component of any central processing unit (CPU), playing a fundamental role in executing arithmetic and logical operations. As the ALU is present in almost all devices, securing it is vital for ensuring overall device safety.
This paper presents the design of a 32-bit ALU using a hardware description language (HDL), specifically Verilog. HDL efficiently illustrates and designs circuit functions and layouts. The approach involves a framework that prioritizes modularity to improve the adaptability and recyclability of the ALUs in various scenarios.
This research introduces a method of enhancing security without affecting the Arithmetic Logic Unit (ALU) functionality. The concept involves incorporating encryption
components at critical points of the ALU to obscure its functions and shield it from possible security breaches, all while maintaining data integrity and minimizing impact on resource usage. Techniques like obfuscation, which have been successfully implemented in low-power circuit designs, reinforce the effectiveness of such security approaches [13][17].
The proposed ALU was verified and analyzed using Xilinx tools, demonstrating successful obfuscation module integration. The analysis revealed minimal area overhead, highlighting the design's efficiency. This implementation underscores the balance between security and performance, making it a valuable contribution to modern hardware design.