Abstract
In recent years, chip design has increased in speed and complexity, which resulted in a significant increase in the power consumption of very-large-scale-integration (VLSI) chips. Therefore, it is required to accurately measure and effectively reduce the power consumption of the design. This project shows the automation of the PowerArtist tool, which is used for early RTL (Register Transfer Level) power and Clock Gate Efficiency (CGE) estimation. The PowerArtist tool is widely used across semi-conductor industries, it provides precise power analysis and suggestions in order to make the design more power friendly while meeting all required functional specifications.