Abstract
The increase in demand of Silicon chips requires manufacturing of millions of units. When these number of units are required to test, better test programs and improvement in testing time are necessary. Different algorithms can be used to reorder patterns to improve test time. Vmin search method provides the capability to find minimum operational voltage (Vmin) for corresponding content (Pattern list or Plist) and test conditions (e.g., frequency). It is a linear method, from fail to pass voltage conditions (either from low to high or from high to low voltage values). We are sorting the patterns according to the frequency of failing and reorder them such that the most failing pattern is moved to the top of the list.
Test time reduction requires substantial effort to ensure a product is enabled for efficient execution meeting factory capacity and cost targets. By reducing time-to-market and improving overall efficiency, semiconductor companies can stay competitive and meet the rapidly changing demands of the market.