Abstract
This project provides a simplified model in Verilog to demonstrate a flow of communication for a neural network chip called CM1K. In this communication model, the HDL acts as a data provider to the chip as well as a controller to channelize the communication flow. Hardware level communication with a non-contemporary technology can be challenging, particularity for someone new to the technology. This project provides a good understanding of the CM1K technology, HDL model for the controller, communication protocol, necessary knowledge of the tools for creating an HDL model and simulation results using ModelSim tool, demonstrating the working of the HDL logical blocks. The HDL model is ASIC agonistic and can be used for further references and research purposes.