Abstract
According to Moore’s law, the number of transistors on integrated circuits (ICs) double approximately every two years. Over the years, this growth in number of transistors has reached to billions of transistors per IC, operating at very high frequencies. However, there are many factors limiting this growth rate including power consumption of high-density high-speed integrated circuits. Various techniques have evolved offering reduction in dynamic power consumption and leakage power. Traditional methods like use of power efficient circuits, parallelism in micro-architectures, along with nontraditional methods such as clock gating, variable supply voltage and frequency scaling are becoming significantly important in lowering dynamic power consumption. The leakage power, which has become more significant in the recent high-density designs, can be reduced by minimizing usage of low threshold voltage cells, adding power gating, back biasing, reducing oxide thickness, and using new devices such as FINFET’s. Design engineers have to consider clock and power gating techniques up front in the design cycle in today’s multi-threshold, multi-oxide, multi-voltage and multi-clock devices. Understanding and implementing power intent at register transfer level (RTL), netlist and PG netlist stages requires additional design verification efforts. In this project, several power reduction and management techniques were studied and applied to an existing System on Chip (SoC) system consisting of an ARM processor, an Ethernet controller, and a DDR controller. Clock and Multi VDD power gating were considered as primary techniques for achieving power reduction. Power intent was created as per the IEEE 1801-2009 Unified Power Format standard. Open source Verilog model of the SoC ARM processor was used as a reference model, along with Synopsys® 90 nm cell library. Synopsys® Electronic Design Automation (EDA) tools were utilized in carrying out simulation, synthesis, and power analysis phases of the project. In addition to implementation of low-power RTL design techniques, use of clock gating, power gating, multi-voltage design partition and multi-threshold voltage cells showed significant improvement in power consumption of the System on Chip (SoC) system used in this work. By considering design issues and verification requirements of these techniques, we developed a power-aware SoC design flow. This enhanced methodology presents a unique approach for effectively incorporating low-power techniques early in the design phase.