Abstract
A ring oscillator is a device whose output oscillates between two voltage levels, which is used for timing and sequencing of logic circuitry. The inverters are attached in a chain with the output of the last inverter fed into the first one. Ring oscillators only require power supplies to operate; oscillation begins spontaneously. The output of every inverter in a ring oscillator changes a finite amount of time after the input has changed. From here, it can be easily seen that adding more inverters to the chain increases the total gate delay, reducing the frequency of oscillation. The period of an actual integrated circuit ring oscillator varies slightly in a random manner due to noise. This variation in oscillator period is called jitter. The primary cause of jitter in high-speed digital systems is usually noise on the power supplies and in the silicon substrate. Thermal noise can also be a source of jitter, but jitter due to thermal noise is typically negligible. This design will specifically aim at reducing jitter due to supply and substrate noise through the use of modified inverter delay cells.