Abstract
As technology advances the physical dimensions on integrated circuits get smaller. This makes the fabrication on the silicon more and more difficult. The semiconductor manufacturing industries have adopted sophisticated methods to fabricate integrated circuits. This introduces new set of failure modes that limits the yield on wafers. As failure modes change, new methods to detect these failures need to be developed. Current methods for checking printability lack sophisticated inter layer checks for detecting more complex failure modes. This project proposes a new method to locate and predict such defects related to Self Aligned Vias (SAV). The project is based on a programming language called Standard Verification Rule Format (SVRF). The method is based on taking into account the effect of 2D geometries and overlay effects.