Abstract
The Dynamic Offset Test Bench (DOTB) is a simulation technique that yields values for the input-referred offset voltage of latching comparators including both static and dynamic effects [2]. This project focuses on an implementation of the DOTB in a 0.18um CMOS silicon integrated circuit. This chip will provide a test vehicle to compare the measured performance of multiple comparators to their simulated performance. Such comparisons will help to validate the DOTB simulation technique and will provide insights into the operation of latching comparators.The comparators to be tested comprise an array of 16 comparators incorporating various intentional imperfections. A separate comparator is also included on chip to allow the DC bias voltages inside the comparator to be measured. It should be noted that the comparator and charge pump circuits were previously designed by other graduate students at Sacramento State [6].This work involved the integration of the comparator array and charge pump into a complete integrated circuit test chip, as well as the design of a 4-to-16 digital decoder, the bias circuits required for the comparator, and two 16-to-1 multiplexers. The top-level design had to accommodate the overall functionality of the various test modes required.Schematics were captured using Cadence Virtuoso, and simulations were performed to verify performance across process, supply voltage, and temperature (PVT) variations using the Mentor Graphics Eldo Spice simulator and showed that the DOTB technique was working well.