Abstract
Recent changes in computation and storage have led to the tremendous growth of neural networks and big data. Analysis of big data has led to achievements such as self-driving cars through advances in algorithms like machine vision. There is a growing need for new hardware approaches and learning algorithms since it will be increasingly difficult for humans to keep up with these new demands using traditional methods of computing. Therefore, this project proposes a custom hardware accelerator to assist with neural network training and to enable parallelization through two neural networks working simultaneously. Software applications make use of hardware accelerators by offloading intense computational workloads. This project highlights the design and implementation of a neural network and presents a method of training the network through a population-based learning algorithm called Particle Swarm Optimization, all in hardware. An essential requirement to achieve a fully functioning neural network in hardware is to use customizable hardware. A digital circuit targeting a field programmable gate array, (FPGA) is a perfect fit for implementing such a system. FPGA allows for reconfiguration of hardware and high parallelization for deployment of custom hardware, along with efficient testing of the design. This project shows the training of the neural network through Particle Swarm Optimization and its design methodology onto FPGA. System Verilog, a hardware description language, and cell libraries from vendors enabled the development of two algorithms, Neural Network (NN) and Particle Swarm Optimization (PSO), to achieve a fully synthesizable design to FPGA. Verification of the custom hardware design was done, and the concept of training a neural network using a population-based algorithm developed on hardware targeting FPGA was shown.