Abstract
Encryption of data has become a necessary practice in our technological society. Encryption tries to ensure protection of important information, corporate secrets, classified information, and private information. Along with protecting data, we need to ensure that the data is coming from an authorized source. Authentication and encryption combined ensure the integrity of the data. Authenticated-encryption has become popular because of the practice of attacks by hackers who are trying to steal information. OCB3 is a new authenticated-encryption mode algorithm developed by Krovetz (1) and Rogaway (2). OCB3 is built from a blockcipher using a counter mode with a nonce. Krovetz and Rogaway compared the algorithm to other encryption algorithms such as GCM (3) and CCM (4). GCM was created into a NIST (5) standard based on research showing it performed better than OCB. It is very similar to OCB3 as they both rely on AES encryption with a counter-mode block cipher. Since GCM is a NIST standard, hardware designers have created optimized solutions for GCM (6). Krovetz and Rogaway’s research shows that OCB is actually better. They made enhancements to OCB in order to improve its performance beyond that of GCM. The current version is OCB3. One of their goals is to show that the hardware approach also performs better. This work presents a hardware model of the OCB3 algorithm in SystemVerilog hardware description language. The proposed model is validated thoroughly using a testbench that utilizes SystemVerilog verification features. The validated design is synthesized using a 90 nm technology library. The electronic design automation tools from Synopsys® Inc. such as VCS simulator and Design-Compiler synthesis tools are used in this work.