Abstract
This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5µm CMOS process technology. This integrated circuit was designed using a 1.5 bit/stage pipelined architecture and uses seven stages, which forms the most critical part of the chip referred to as the ‘pipeline core’. From the information received from the advisors of the previous team, the comparator included an adjustable reset time design-for-test (DFT) feature, but test results indicated minimal adjust range of the reset time.My part of this project was focused on the diagnosis and redesign of the comparator located within the Sub-ADC of the pipeline core.