Abstract
The goal of this project is to design and implement FPGA design of Daubechies lifting scheme for audio compression and reconstruction. The design approach is to use top down hierarchical design. The algorithm implemented performs compression and reconstruction for three levels. Daubechies scheme is recursive process in which output of previous level is input to another level and so forth. It was challenging to implement this project, as it needed lots of research effort for both software algorithm and hardware interface implementation. The completely audio compression system was implemented initially with Matlab and then with Verilog Hardware description language and emulated on Cyclone II FPGA of Altera DE2 kit. The algorithm generates satisfactory audio decompressed outputs.