Low-latency systems require fast and accurate timestamping to support time-critical functional control and benchmarking in industrial and autonomous applications. Software timestamping acquired at the OS level are less than ideal due to the scheduler jitter, cache effects, and queuing delays. This project presents an FPGA-based, lightweight UDP/IP packet timestamping system deployed on a Digilent Nexys A7 (Artix-7) board. Received Ethernet frames are parsed in hardware, and timestamps come from an internal free-running counter serially output via UART for logging and analyzing. On a 100 Mb/s link with a 32-byte UDP payload, the timestamper achieves deterministic behavior with serialization windows of 2.48 µs, matching the theoretical wire rate, versus the software jitter standard deviation of 344 µs. Thus, showing the lower latency of hardware timestamping on an FPGA versus software timestamping.
- FPGA-Based design and implementation of a lightweight UDP timestamping system
- Zaid Elias
- Zahra Najafi (Advisor)Preetham Kumar (Committee Member)
- Electrical Engineering
- Master of Science (MS); Electrical and Electronic Engineering; California State University, Sacramento; 12/05/2025; 2025
- California State University, Sacramento
- 10/13/2026
- 99258309230301671; https://hdl.handle.net/20.500.12741/rep:14433
- Masters Project
- English
- 58