Abstract
NAND flash memory is a storage medium composed of floating-gate transistors. Floating-gate transistors have some semblance to a MOSFET (electrically) with the exception of its floating gate. Data (1’s and 0’s) can be stored by modulating the amount of charge stored in the floating gate. User data loss can occur, if the amount of charge stored on the floating gate varies beyond certain bounds due to any number of flash wear mechanisms. Some examples of flash wear mechanisms include: temperature stresses, usage model driven stress (erase, write, read), and field disturbances. Each have an impact on our ability to accurately read the desired data; this is commonly known as readability windows or read margins. As flash devices are subjected to these failure mechanisms, the readability window decreases; and in some cases, the effects are permanent (for example: cell wear due to program/erase cycling). With industry pushing for smaller technology nodes and increased bits/cell, the mechanisms are magnified and will put an increased demand for stronger ECCs.