Abstract
The focus of this project was to design two comparators for an asynchronous level crossing ADC designed in a 90nm CMOS process by team of graduate students at Sacramento State. The first comparator had to be fast enough to detect a typical biomedical signal such as a human heartbeat, while minimizing power consumption. In this LC-ADC, that required a comparison delay of no more than 300ns and power consumption of no more than 250nW. The second comparator could be slower with a comparison time as high as 700ns, but must dissipate only 170nW. In addition, this comparator uses hysteresis to prevent undesirable chatter in its output which would waste power. A current DAC was included to allow the amount of hysteresis used to be adjusted. Both comparators were designed in a 90nm CMOS process, and use a power supply voltage of only 800mV to reduce power consumption. Both comparators were simulated across process, supply voltage, and temperature (PVT) variations to verify performance.