Abstract
To design for high performance circuits, a precision clock with low jitter is needed to meet the high frequency requirements. A phase-locked loop (PLL) is used to achieve the required low jitter. The phase-locked loop architecture can be simplified down to a few major blocks: a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider. The voltage-controlled oscillator (VCO) which is the subject of this report uses a ring oscillator that incorporates delay cells using cascode voltage switch logic with data anticipation in the differential inverter design. The data anticipation is achieved by using two PMOS pull up transistors that are controlled by the previous delay cell, thereby increasing the switching speed of the ring oscillator. The cascode voltage switch logic uses complementary signals to minimize jitter. The frequency of the oscillator is controlled by varying the VCO supply voltage, which gives a wide range of frequencies.