Abstract
Today we live in an age where data security in digital communication has become an important requirement. The need for privacy and protection of data has made major companies take appropriate actions like recent addition of end-to-end encryption by WhatsApp for its over billion users. There are both software and hardware approaches to encrypt messages with former being more flexible but less efficient than latter. Moreover, hardware solutions are most advisable for portable devices [1]. In this project, a hardware accelerator for AEGIS128L encryption algorithm is presented for mobile devices. The accelerator was designed considering power efficiency as one of the primary goals, since mobile devices operate on battery supply. Different power saving techniques like parallel design, clock gating, power gating and multi-threshold voltage cells were used to achieve this goal. Other important factors considered were speed and area. The project encompassed power aware hardware implementation of AEGIS128L, modeling it in SystemVerilog hardware description language (HDL), verifying it using a layered test bench, synthesizing it using 90nm cell library and finally performing power estimation. In the power estimation, we used the gate-level netlist generated during synthesis and the switching activity of the netlist during simulation to get an accurate estimation of power usage. Synopsys Electronic Design Automation (EDA) tools like VCS simulator, Design Compiler synthesis, and Power Compiler tools were used in this work. Power consumption of the proposed design improved considerably throughout the project phases. The proposed design required 7.6% less power compared to a non-power aware design in the normal operating mode. The power saving during the sleep mode was 68%. The design supports data rate of 1.6 Gigabytes per second.