Abstract
The design and simulation of a phase frequency detector and a charge pump for a low-jitter, high-frequency phase-locked loop in 0.18μm CMOS are explored. The NAND-based sequential phase frequency detector is shown to accurately compare the phase differences between two clock signals without the presence of a “dead zone”. The charge pump exhibits excellent linearity over a wide range of loop filter voltages as well as with varying differences in phase. A minimum phase offset of 2.45º is achieved by the use of current matching techniques and differential input transistors that are constantly kept in saturation. A new implementation of a common clamping technique has also been used in order to eliminate non-monotonicity in the charge pump output.