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Design of a fully-differential dual-slope analog-to-digital converter
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Design of a fully-differential dual-slope analog-to-digital converter

Angela Marie Galvez
Master of Science (MS), California State University, Sacramento
05/23/2019

Abstract

12-bit synchronous counter IC design CMOS ADC OTA CMFB Folded-cascode Circuit Wide-swing bias Common-mode feedback Latching comparator Integrator Microelectronic design Digital design Analog design Operational transconductance amplifier
Dual-slope analog-to-digital converters (ADCs) are known for their high accuracy, but slow conversion times. The objective of this project was to design a 12-bit dual-slope analog-to-digital converter in a 0.5 µm CMOS process which rejects 60 Hz noise and employs fully-differential circuits. Each circuit within the ADC was designed and simulated using the Mentor Graphics computer-aided design (CAD) integrated circuit (IC) design tools in order to meet a set of target specifications.
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