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Design of a Bubble Suppress Circuit and ROM Encoder Logic for a 6-bit Flash ADC in 0.18um CMOS
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Design of a Bubble Suppress Circuit and ROM Encoder Logic for a 6-bit Flash ADC in 0.18um CMOS

Rommel Emmanuel
California State University, Sacramento
Master of Science (MS), California State University, Sacramento
03/25/2022
Handle:
https://hdl.handle.net/20.500.12741/rep:2339

Abstract

ADC Binary Bubble Suppress Circuit CMOS Error correction ROM encoder
The objective of this project was to design and simulate a bubble suppress circuit and a ROM encoder for a 6-bit flash analog-to-digital converter (ADC) in 0.18μm CMOS operating at a clock frequency of 750 MHz. This report discusses the architecture chosen for these circuits, their transistor level design, and the simulation results obtained across process, supply voltage, and temperature (PVT) variations.
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