Abstract
The binary addition and subtraction of the double precision floating-point number are the integrated parts of the arithmetic logic unit in many processors. This project is to design the addition and subtraction of two double precision floating-point numbers with pipelined hardware. Leading One Detector was applied to normalize the result generated from adding or subtracting the mantissa bits. In addition, the output was shifted by the 55-bit Barrel Shifter and converted to the IEEE-754 double precision floating point format. This work used the Synopsys tool for design and simulation. Different test cases were studied and verified for both the addition and subtraction operations.