Abstract
Electrocardiograph (ECG) recorders are medical devices used to measure and record electrical signals generated by the activity of the heart in the human body. Doctors use the data from an ECG to detect signs of cardiac disease in a patient. The input signal to an ECG recorder is a low-frequency analog signal that is very small in amplitude, on the order of only 1-10mV. So the analog front end (AFE) for an ECG recorder must first amplify this small signal, while adding as little noise as possible. The focus of this project is to design and simulate a low noise amplifier (LNA) for the AFE of an ECG integrated circuit (IC) in a 0.18μm CMOS process. This LNA must achieve a high common-mode rejection ratio (CMRR) to reject ambient noise in the surrounding environment, while providing voltage gain and minimizing the noise that it adds to the signal. The amplifier presented here achieves these goals while also minimizing the amount of power used. The circuit accomplished the preceding by means of a current-balancing technique in its feedback circuit. The performance of this LNA was verified through simulations across process, supply voltage, and temperature (PVT) variations using professional IC design CAD tools.