Abstract
Smart Devices and the need for intelligent systems has brought about a revolution in Technology. With devices getting smaller, yet more effective, there is a constant need for research and development of smart system designs. One such entity that has taken the world of technology by storm, is the need for smart sensor hubs that support smart wearable devices. The sensor hubs today, need to be designed for low power systems, without compromising high performance. Smart wearable devices are intelligent enough to measure heart rates, and mobile phones are intelligent enough to provide health tips for a better living. Such advancements have been made possible with continuous efforts to improve the device performance by improving the computational ability of these systems to effectively collect and manage all the sensor data. These devices come with an added need for high power application processors and longer battery runtimes. This requirement in turn, has opened the doors for more computational abilities for handling the data provided by various sensors such as accelerometers, gyroscopes and many more. The main scope of this project was to study the need for such smart systems, and in turn develop one such system which is power efficient, yet effective in terms of performance. The main idea was to understand the communication interface between a sensor hub, which can typically be classified as an I/O Device and the main controller such as the ARM Cortex M0. The scope has been extended to implement the system with a memory comprising of a 32KB LI cache. This project revolves around the design of a System on Chip, where we will design and implement a sensor hub interface, which is compatible with communication protocols for low frequency, high speed I/Os such as UART or AMBA APB-SPI or a high speed I2C. Since the sensor hub is mainly used for low frequency applications, the interface would be of low speed characteristics. The master device would be a Cortex M0 processor, an ARM empowered device, comprising of a 32-bit L1 cache and 8KB main memory. The connecting devices to the sensor controller would be a proximity sensor, a touch sensor and a gyroscope. For power optimization purposes, the sensor hub would comprise of its own power management unit. The front-end design and simulation of the component would be done using Verilog on a VCS platform, offered by Synopsys and the Integrated Design Environment being Linux. Validation will involve random and corner cases, to ensure the functionality will be verified with complete coverage. This marks the last phase of the project.