Abstract
Protecting sensitive information is a critical responsibility for every federal organization, especially when it comes to securing electronic data systems. To help with this, the Advanced Encryption Standard (AES) was developed [1][2]. AES offers a strong cryptographic method that federal agencies can use to safeguard sensitive data, whether it's being transmitted across networks or stored in vulnerable locations [2].
Encryption plays a major role across a variety of applications and systems. How AES is used and integrated often depends on factors like the type of computer system and its related components [3]. Generally, encryption is used either to secure data moving between two points or to protect data stored on physical media that might be at risk of theft.
In communication security, data is encrypted before it's sent and decrypted once it reaches its destination. Similarly, file security involves encrypting data when it's saved and decrypting it when it's accessed again. A key part of both processes is that the encryption key must be present at both ends — for the sender and the receiver — at the same time.
In this project, we focus on implementing both the encryption and decryption stages of AES for two key sizes: 128-bit and 192-bit [4]. Our design is developed using Verilog HDL, with a special focus on comparing the performance of the two key lengths, particularly in terms of latency. The goal is to achieve high-speed, low-latency encryption and decryption to boost the overall efficiency and performance of data security solutions.