Abstract
In this project CVSD Decoder design, the implementation of design was done on ALTERA DE2 board. The DE2. board provides many hardware resources such as, Cyclone II 2C35 FPGA, Spansion S29AL032D flash memory, Wolfson WM8731 24-bit sigma-delta audio CODEC IC, IS42S16400L SDRAM, switches and LEDs. In this project, FPGA is used for loading hardware design; 4 MB Flash is used for non-volatile storage purpose and 8 MB SDRAM for making faster operation and saving processed data. CODEC IC has Microphone In, Line In and Line Out, which are used for getting 16-bit digital audio data from analog audio and for again for playing sound from decoded digital data. The sample rate is adjustable from 8 KHz to 96 KHz by using I2C bus in DE2 board, which in turn can help me to control volume. Switches and LEDs are used for inputs and outputs respectively. This chip Provides Microphone In, Line In and Line Out connectors.
In CVSD project, there are two parts encoder and decoder. Encoder takes 16-bit data and encodes it to 2-bit data and Decoder takes 2 bit encoded data and generates 16-bit data by decoding it. My focus in this project is on decoder part. CVSD Decoder decodes 16-bit data using 2 bit signed data. Decoder calculates new data using previous data value and step size. Step size is variable in this decoding method, it keep track of last four input data and if it is same then step size will be incremented by min step size otherwise it will be calculated using previous step size and step decay, so the step size is variable in this CVSD encoding decoding method.