Abstract
Comparators are widely used in mixed-signal systems. They are an essential building block of any analog-to-digital converter architecture. Regenerative comparators are typically used in high-speed analog-to-digital convertor designs. This particular architecture has two main characteristics that make it differentiable from the other architectures. First is the positive feedback during the regenerative phase to achieve high gain and the second is the cancellation of the memory of previous comparison results during the reset phase. A behavioral model of any circuitry block is always helpful, before creating the actual design, to understand the tradeoffs during system design. Verilog-AMS provides an extended capability to model any analog or digital block, so as to seamlessly integrate the behavioral block into the actual design consisting of a combination of analog and digital blocks. A mapping between the analog and digital domains enhances the (re)usability of designs for mixed-signal blocks. Since Verilog-AMS actively supports the mixed-signal approach, the interchange of digital and analog blocks is straightforward. This work will result in a behavioral model for a regenerative comparator written in Verilog-AMS. The project presents the behavioral model of a regenerative comparator written in Verilog-AMS. The model is simulated using the time-windowing function to find the sensitivity of the comparator to pre- and post-clock inputs. The key specifications described in [3] by Thomas Matthews will be used to compare Verilog-AMS behavioral model circuit simulation results with analytical results.