Abstract
Phase Locked Loops (PLLs) are increasingly becoming an essential component of today's electronic systems; however, simulation of PLLs poses a serious problem as standard simulators consume a large amount of CPU time. This project presents a detailed analysis of PLL simulation using standard simulation tools and compares the results to a newly devised PLL simulation tool, TOPS. Beginning with a mathematical analysis of loop filter to deduce the control and capacitor voltage, the project demonstrates the output response of PLL at various inputs using SPICE-level simulation (PSpice) and MATLAB SIMULINK to verify the TOPS results. A few standard tests to PLL measure the accuracy and efficiency of TOPS as compared to MATLAB SIMULINK very clearly shows the improved performance of TOPS in the simulation of PLL systems. The motivation for this project comes from the need to develop a fast and versatile PLL simulation tool. This tool will greatly reduce the design cost in the industry. It will also make it easier to diagnose and solve problems in PLL circuit designs.