Abstract
Current Mode Logic buffers are based on the MOS differential amplifier circuit. Since CML buffers utilize a differential circuit topology, they are less vulnerable to common-mode noise than standard CMOS buffers. CML buffers are able to operate in higher frequency ranges than standard CMOS buffers, which makes them the optimum choice as output drivers for high-speed integrated circuits. The process of designing a tapered CML buffer chain is explored in this paper, including all important design issues. For this project, a tapered CML buffer chain was designed for a 6-bit interpolating flash analog-to-digital converter operating at 1 GHz.