Abstract
A phase-locked loop is needed on nearly every integrated circuit to align the phase and frequency of the clock created by the on-chip oscillator to an external reference clock. This project was to design and simulate a programmable frequency divider in 0.18um CMOS for an all digital phase-locked loop integrated circuit. The frequency divider can provide one of four different output frequencies, based on the input control bits. Schematics for the programmable frequency divider were designed using Cadence Virtuoso, and simulations were performed using the Spectre simulator. Simulations were run for both typical and worst-case variations of process, supply voltage, and temperature.