Abstract
The increasing need for protecting data communication in computer networks has led to development of several cryptography algorithms. The Advanced Encryption Standard (AES) is a computer security standard issued by the National Institute of Standards and Technology (NIST) intended for protecting electronic data. Its specification is defined in Federal Information Processing Standards (FIPS) Publication 197. The AES cryptography algorithm can be used to encrypt/decrypt blocks of 128 bits and is capable of using cipher keys of 128, 196 or 256 bits wide (AES128, AES196, and AES256). The Advanced Encryption Standard can be implemented in either software or hardware. Hardware acceleration is the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higher performance in today’s heavily loaded communication networks, utilization of hardware accelerators for cryptography algorithms is more efficient. In this project, a hardware implementation of the AES128 encryption algorithm was proposed. A unique feature of the proposed pipelined design is that the round keys, which are consumed during different iterations of encryption, are generated in parallel with the encryption process. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintext block. This leads to an increase in the message encryption throughput. The proposed pipelined design was modeled and validated in SystemVerilog hardware description language. The testbench developed for validating the design kept track of Functional Coverage to make sure the design is thoroughly verified. The design was validated using the Synopsys VCS tool and synthesized using the Synopsys Design-Compiler tool. The gate level netlist generated during the synthesis phase using the LSI_10K technology library was capable of operating at 40MHz frequency. We expect the timing and area of the gate level netlist to improve if a more efficient technology library file is used for synthesis. Finally, to get an estimate of the speed gain by the hardware implementation, a virtual system was created using the Virtutech® Simics™ software to emulate the execution of a “C” program that implements the AES128 encryption in software. The Simics virtual system utilized in this project is based on Intel’s x86 architecture with the 440BX chipset and has a 2GHz Pentium4 processor. The statistics gathered from the virtual system showed that it would take more than 30,000 CPU cycles to encrypt a block of plaintext, assuming one clock per instruction. The results indicate that the hardware implementation proposed in this project is at least 60 times faster than the software implementation.