Abstract
Hacking and Phishing are major threats in today’s informational world. Information security is a major concern for Information Technology (IT) specialists. Hackers and other untrusted parties try to access the confidential information using different hacking schemes. The only stable and long-term solution to security threats is enforcing a strong and complex method of identity assurance. To achieve this, IT specialists incorporate different encryption techniques. In general, encryption refers to transforming the information into ciphered text using ciphers (algorithms). The ciphered text is readable, and only authenticated parties can decipher it. Hence, encryption is one of the major security solutions. Encryption involves a number of algorithms, one of which is cryptographic hashing. To enhance the performance of software algorithms, the developers rely on hardware accelerators. A hardware accelerator is a specific hardware unit apart from the CPU that performs a dedicated software or algorithmic implementation. In this project, a hardware implementation of a hashing algorithm known as VHASH is proposed. It was designed for exceptional performance on the systems that support 64-bit multiplication efficiently [5]. The hardware implementation of the VHASH algorithm involved modeling the algorithm in System Verilog hardware description language, validating and synthesizing it using a current hardware cell library. The testbench developed for verifying the design used System Verilog Functional Coverage to make sure the design was thoroughly verified. Verification was performed on Synopsys VCS® tool. The expected results used in validating the implementation were generated based on an existing python code for VMAC from [3]. The final phase of the project involved synthesizing the System Verilog model of VHASH algorithm towards LSI_10k technology library.