Abstract
The reference voltage generator is an important circuitry block in pipelined analog-to-digital converters (ADCs). The function of the reference generator is to provide accurate reference voltages to the ADC which are compared to the unknown input signal in order to convert analog data into digital. To maintain sufficient accuracy, the reference voltage generator often consumes a substantial amount of area and power in relation to other circuits on the integrated circuit. This project focuses on reducing the power and area required by reference voltage generators used for pipelined ADCs while maintaining the required accuracy. To minimize error in the ADC output, traditional reference voltage generator designs used for pipelined ADCs strive to keep variations in the reference voltages much less than a least-significant bit (LSB). This is accomplished using two different design methods. The first method is to use large bypass capacitors on the reference voltage outputs to minimize the glitches seen in the reference voltages when the residue stage capacitors connect to these outputs. The second method is to design the reference voltage output buffers to have a very low output resistance to prevent errors due to the average current drawn from the buffer. Both of these methods require a large amount of silicon area, and the second also requires a substantial amount of power to achieve the low output resistances required. This project proposes a design for the reference voltage generator that can save substantial area and power compared to the previously described traditional design. Rather than minimizing variations in the reference voltages, the proposed design described in this report allows the reference voltages to vary much more as long as they quickly return to their correct values. Analysis shows that this method requires far less area and power than traditional reference voltage generator designs. A second design technique also examined here employs signal-dependent charge cancellation. Through the use of replica residue stages, the charge injected by the residue stages into the reference voltage generator outputs can be made signal independent, thereby eliminating this source of error in the ADC output codes. In combination with the first design improvement, this signal-dependent charge cancellation allows the requirements on the reference voltage generators to be further relaxed, thereby saving even more area and power. This project presents an accurate 8-bit, 1.5-bit/stage pipelined ADC Matlab computer model that has been derived from a pipelined ADC Matlab model previously developed by Professor Perry Heedley. This new model was used to verify the proposed reference voltage generator design, as well as the signal-dependent charge cancellation technique. Analysis of the new reference voltage generator design and the signal-dependent charge cancellation technique was also performed through Spice simulations of a previously designed 8-bit, 1.5-bit/stage pipelined ADC previously designed by a team of graduate students at CSU, Sacramento. The end result was a design for accurate reference voltage generators for pipelined ADCs that have greatly reduced area and power when compared to conventional designs.