Abstract
The most widely used design for a memory cell in Static Random-Access Memory (SRAM) today is the 6T bit cell, which uses six transistors to store a single bit of binary data. This project was aimed at investigating a new structure proposed for SRAM bit cells [9], which uses seven transistors to save power, and comparing it to the traditional 6T SRAM bit cell. The criteria used to evaluate performance included the write and read times, the amount of power consumed, and the static noise margin (SNM) for both bit cell designs. Simulations were run for worst-case operating conditions with a slow-slow process, high temperature, and low voltage supply, as well as for other process, supply voltage and temperature (PVT) conditions.