Time complexity of systolic array testing

N Faroughi

doi:10.1109/DFTVS.1992.224373

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Conference proceeding

Time complexity of systolic array testing

N Faroughi

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp.100-108

1992

DOI: https://doi.org/10.1109/DFTVS.1992.224373

Handle:

https://hdl.handle.net/20.500.12741/rep:5880

Abstract

Computer science

Pipelines

Communication system control

Controllability

Systolic arrays

Circuit faults

Circuit testing

Observability

The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maximum regeneration distance be applied last. For the non-OISAs, reconfigurable functional routers in each cell is proposed. A non-OISA can be reconfigured into one or more OISAs.< >

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Title: Time complexity of systolic array testing
Creators: N Faroughi - Dept. of Comput. Sci., California State Univ., Sacramento, CA, USA
Academic Unit: Computer Science Department
Publisher: IEEE Comput. Soc. Press
Publication Details: 1992
Identifiers: 99257847157601671; https://hdl.handle.net/20.500.12741/rep:5880; https://doi.org/10.1109/DFTVS.1992.224373
Language: English

Time complexity of systolic array testing

Abstract

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