Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

Kevin B Geoghegan; P. L Heedley; T. W Matthews; S Michael

doi:10.1109/MWSCAS.2011.6026340

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Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

Kevin B Geoghegan, P. L Heedley, T. W Matthews and S Michael

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp.1-4

08/2011

DOI: https://doi.org/10.1109/MWSCAS.2011.6026340

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https://hdl.handle.net/20.500.12741/rep:5070

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The design of a CMOS track-and-hold amplifier (THA) for a 6-bit 1-GS/s interpolating flash ADC is presented. Since the goal of the overall project was to determine the performance of a new ADC calibration architecture, the THA was prohibited from being the limiting factor in the performance of the ADC; consequently the THA was required to have at least 56dB of signal-to-noise and distortion ratio (SNDR) at the Nyquist frequency. The THA architecture, design methodology, and supporting simulation results will be presented.

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Title: Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC
Creators: Kevin B Geoghegan - Dept. of Electr. & Comput. Eng., Naval Postgrad. Sch., Monterey, CA, USA
P. L Heedley - Dept. of Electr. & Electron. Eng., California State Univ., Sacramento, CA, USA
T. W Matthews - Dept. of Electr. & Electron. Eng., California State Univ., Sacramento, CA, USA
S Michael - Dept. of Electr. & Comput. Eng., Naval Postgrad. Sch., Monterey, CA, USA
Academic Unit: Electrical Engineering
Publisher: IEEE
Publication Details: 08/2011
Identifiers: 99257847445601671; https://hdl.handle.net/20.500.12741/rep:5070; https://doi.org/10.1109/MWSCAS.2011.6026340
Language: English

Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

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