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An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB
Conference proceeding

An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB

V Savengsveksa, P.L Heediley, T Matthews, K Ahmad and J Negrete
48th Midwest Symposium on Circuits and Systems, 2005, pp.409-412 Vol. 1
2005
DOI: https://doi.org/10.1109/MWSCAS.2005.1594124
Handle:
https://hdl.handle.net/20.500.12741/rep:4450

Abstract

Energy consumption Circuits Capacitors Voltage CMOS technology Sampling methods Design for testability Logic testing Analog-digital conversion Clocks
This paper presents an 8-b 20-Msample/s pipelined analog-to-digital converter (ADC) designed in 0.5-mum CMOS technology. On first silicon this converter achieved 7.8 effective-number-of-bits (ENOB), a peak differential-non-linearity (DNL) of -0.36LSB and integral-non-linearity (INL) of 0.35LSB

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