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A framework for automatic CMOS OpAmp sizing
Conference proceeding

A framework for automatic CMOS OpAmp sizing

P K Meduri and S K Dhali
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, pp.608-611
MWSCAS 2010, 53rd (Seattle, WA, 08/01/2010 - 08/04/2010)
08/2010
DOI: https://doi.org/10.1109/MWSCAS.2010.5548899
Handle:
https://hdl.handle.net/20.500.12741/rep:7557

Abstract

Semiconductor device modeling Process design Solid modeling Design automation Circuit simulation Computational modeling DH-HEMTs Analog circuits Equations Design optimization
The problem of automatic CMOS OpAmp sizing is addressed. Given the specifications and the netlist of the OpAmp, our approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The approach is based on generating an initial first-order design by using geometric programming and then refining it using simulations. Device-level simulations performed on a two stage OpAmp prove the efficacy of our approach.

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