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A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps
Conference proceeding

A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps

P K Meduri and S K Dhali
2011 24th Internatioal Conference on VLSI Design, pp.100-105
01/2011
Handle:
https://hdl.handle.net/20.500.12741/rep:7948

Abstract

Accuracy Programming Data models Mathematical model Integrated circuit modeling Equations Optimization

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