Sign in
Back
A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-/spl mu/m CMOS
Conference proceeding

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-/spl mu/m CMOS

P.L Heedley, K.C Dyer, T.W Matthews, P Isakanian and Chuc Chuc Thanh
48th Midwest Symposium on Circuits and Systems, 2005, pp.1003-1006 Vol. 2
2005
DOI: https://doi.org/10.1109/MWSCAS.2005.1594273
Handle:
https://hdl.handle.net/20.500.12741/rep:3185

Abstract

Circuit topology Capacitors Fingers Feedback Switches Bandwidth Sampling methods Decoding Copper Clocks
An 8-b pipelined ADC constructed in 0.13-mum CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125MS/s while consuming 30mW from 1.8-V and 1.2-V supplies. Active area is 0.4mm 2

Metrics

6 Record Views

Details